User manual TEKTRONIX BERTSCOPE BSA DATASHEET

[. . . ] Bit Error Rate Tester BERTScope® BSA Series Data Sheet Jitter Tolerance Compliance Template Testing with Margin Testing Physical Layer Test Suite with Mask Testing, Jitter Peak, BER Contour, and Q-factor Analysis for Comprehensive Testing with Standard or User-defined Libraries of Jitter Tolerance Templates Integrated Eye Diagram Analysis with BER Correlation Optional Jitter Map Comprehensive Jitter Decomposition ­ with Long Pattern (i. e. PRBS-31) Jitter Triangulation to Extend BER-based Jitter Decomposition Beyond the Limitations of Dual Dirac TJ, DJ, and RJ for a Comprehensive Breakdown of Jitter Subcomponents Patented Error Location AnalysisTM enables Rapid Understanding of your BER Performance Limitations and Assess Deterministic versus Random Errors, Perform Detailed Pattern-dependent Error Analysis, Perform Error Burst Analysis, or Error-free Interval Analysis Features & Benefits Pattern Generation and Error Analysis, High-speed BER Measurements up to 26 Gb/s Integrated, Calibrated Stress Generation to Address the Stressed Receiver Sensitivity and Clock Recovery Jitter Tolerance Test Requirements for a Wide Range of Standards Sinusoidal Jitter to 100 MHz Random Jitter Bounded, Uncorrelated Jitter Sinusoidal Interference Spread Spectrum Clocking PCIe 2. 0 Receiver Testing F/2 Jitter Generation for 8xFC and 10GBASE-KR Testing Electrical Stressed Eye Testing for: PCI Express 10/40/100 Gb Ethernet SFP+/SFI XFP/XFI OIF/CEI Fibre Channel SATA USB 3. 0 Applications Design Verification including Signal Integrity, Jitter, and Timing Analysis Design Characterization for High-speed, Sophisticated Designs Certification Testing of Serial Data Streams for Industry Standards Design/Verification of High-speed I/O Components and Systems Signal Integrity Analysis ­ Mask Testing, Jitter Peak, BER Contour, Jitter Map, and Q-factor Analysis Design/Verification of Optical Transceivers Data Sheet Linking Domains Eye diagrams have always provided an easy and intuitive view of digital performance. It has been harder to tie this directly with BER performance, as the instruments that provide views of each have been architected in fundamentally different ways. Eye diagrams have been composed of shallow amounts of data that have not easily uncovered rarer events. [. . . ] Operation takes less than 10 seconds www. tektronix. com 9 Data Sheet Pattern Generator Ancillary Connections Front-panel Pattern Generator Connections External Clock Input Characteristic Description Rear-panel Pattern Generator Connections Pattern Start Input Characteristic Description Allows use of an external clock source to clock the BERTScope. Models equipped with stress are able to add impairments to incoming clock, including when external signal has Spread Spectrum Clocking (SSC) in excess of 5000 ppm imposed on it. Frequency Range BSA85C 0. 1 to 8. 5 GHz BSA125C, CPG 0. 1 to 12. 5 GHz BSA175C, CPG 0. 5 to 17. 5 GHz BSA260C, CPG 1 to 26 GHz Nominal Power 900 mVp-p (+3 dBm) Maximum Power 2. 0 Vp-p (+10 dBm) Return Loss Better than ­6 dB Interface 50 SMA female, DC coupled into selectable termination voltage HF Jitter (Option STR Only) Characteristic Description For users wanting to synchronize patterns of multiple data streams from multiple instruments simultaneously. Logic Levels LVTTL (<0. 5 V Low, >2. 5 V High) Threshold +1. 2 V typical Max Nondistructible Input ­0. 5 V to +5. 0 V Range Minimum Pulse Width 128 serial clock periods Maximum Repetition Rate 512 serial clock periods Interface SMA female, >1 k impedance into 0 V Page Select Input Characteristic Description One of two jitter insertion inputs. Frequency Range DC to 1. 0 GHz Jitter Amplitude Range Up to 0. 5 UI max Input Voltage Range 0-2 Vp-p (+10 dBm) for normal operation 6. 3 Vp-p (+20 dBm) max nondestructive input Data Rate Range Up to 8. 5, 11. 2 (BSA125C, CPG, only), 17. 5, or 22 Gb/s Interface SMA female, 50 , DC coupled into 0 V Sub-rate Clock Output Characteristic Description In A-B Page Select mode, allows external control of pattern. Software control over rising or falling edge trigger, continuous Pattern B after completion of Pattern A, or run B only once before reverting back to A. Logic Levels LVTTL (<0. 5 V Low, >2. 5 V High) Threshold +1. 2 V typical Max Nondistructible Input ­0. 5 V to +5. 0 V Range Minimum Pulse Width 1 pattern length Interface SMA female, >1 k impedance into 0 V Sinusoidal Interference Output (Option STR Only) Characteristic Description SI output from internal generator. Frequency Range 0. 1-2. 5 GHz 0-3 Vp-p Output Voltage 0-3 Vp-p Interface Low-frequency Jitter Input (Option STR Only) Characteristic Description BERTScope standard models have clock divided by 4. Frequency Range 0. 125 to 3. 125 GHz (12. 5 GHz with Option STR) Amplitude Range 1 Vp-p, nominal, centered around 0 V Transition Time <500 ps Interface SMA female, 50 , DC coupled into 0 V Trigger Output Characteristic Description Provides a pulse trigger to external test equipment. Pattern Mode: Pulse at a programmable position in the pattern (PRBS), or fixed location (RAM patterns) Stress modulation added on models so equipped, when enabled. Minimum Pulse Width 128 Clock Periods (Mode 1) 512 Clock Periods (Mode 2) Transition Time <500 ps Jitter (p-p, data to trigger) <10 ps, typical (BSA175C/CPG, BSA260C/CPG) >300 mVp-p, center at 650 mV Output Levels Interface 50 SMA female Allows use of external low-frequency jitter source to modulate the stressed pattern generator output. Frequency Range DC to 100 MHz Jitter Amplitude Range Up to 1. 1 ns, can be combined with other internal low-frequency modulation Input Voltage Range 0-2 Vp-p (+10 dBm) for normal operation 6. 3 Vp-p (+20 dBm) max nondestructive input Data Rate Range Up to 8. 5 Gb/s (BSA85C/CPG), 12. 5 Gb/s (BSA125C/CPG), 17. 5 Gb/s (BSA175C/CPG), and 22 Gb/s (BSA260C/CPG) Interface SMA female 50 , DC coupled into 0 V Low-frequency Sinusoidal Jitter Output (Option STR Only) Characteristic Description To allow phasing of two BERTScopes together, in-phase or anti-phase. Frequency As set for internal SJ from GUI Amplitude 2 Vp-p, centered at 0 V Interface SMA female 10 www. tektronix. com Bit Error Rate Tester -- BERTScope® BSA Series Reference Input Characteristic Description To lock the BERTScope to an external frequency reference from of another piece of equipment. Frequency 10, 100, 106. 25, 133. 33, 156. 25, 166. 67, or 200 MHz Amplitude 0. 325 to 1. 25 Vp-p (­6 to +6 dBm) Interface 50 SMA female, AC coupled Reference Output Characteristic Description Available divide ratios from clock-related output, by bit rate, using the internal clock, BSA85C***. Provides a frequency reference for other instruments to lock to. Configuration Single Ended (Ref-Out not used) (BSA125C, CPG) Differential Frequency 10, 100, 106. 25, 133. 33, 156. 25, 166. 67, or 200 MHz Amplitude 1 Vp-p (+4 dBm) nominal, each output, (2 Vp-p differential) Interface 50 SMA female, AC coupled BSA125C, CPG, BSA175C, CPG, and BSA260C, CPG Clock Path Details BSA85C, CPG Functional block diagram of the clock path for models with stress capability, BSA85C/CPG, BSA125C/CPG, BSA175C/CPG, BSA260C/CPG. * This output can also provide a full-rate jittered clock. *** All listed ratios available for an external clock input over entire bit rate range, limitations for internal clock only. Operation below this rate will be uncalibrated. Functional block diagram of the clock path for models with stress capability, BSA85C/CPG. The BSA125, BSA175, and BSA260 models use an internal Double Data Rate (DDR) architecture to operate at data rates 11. 2 Gb/s. When operating at 11. 2 Gb/s or higher data rate, the clock output will be 1/2 the data rate. When full rate is selected, the pattern generator will operate in DDR mode when the input clock frequency is 11. 2 GHz or higher. External clock will be output at 1/2 rate when half rate is selected, or when full rate is selected and clock rate is 11. 2 GHz. The minimum data rate specified for the main clock output is 500 Mb/s. Output will be uncalibrated when operated at divided rates lower than 500 Mb/s. www. tektronix. com 11 Data Sheet Available Multi-rate and Sub-rate Divider Ratios for Main Clock Output, BSA125C, CPG, BSA175C, CPG, and BSA260C, CPG Models Data Rate (Gb/s) Ratios for Main Clock Out Ratios for Sub-rate Clock Out*3 Pattern Generator Stressed Eye Flexible, integrated stressed eye impairment addition to the internal or an external clock Easy setup, with complexity hidden from the user with no loss of flexibility Verify compliance to multiple standards using the BERTScope and external ISI filters. [. . . ] Preprogrammed formulas for standards such as PCI Express and USB 3. 0 are included. *7 PatternVu operates at data rates of 900 Mb/s and higher. Testing to T11. 2 MJSQ BERTScan methodology (also called `Bathtub Jitter') Deep measurements for quick and accurate extrapolation of Total Jitter at user-specified level, or direct measurement Separation of Random and Deterministic components, as defined in MJSQ As-needed delay calibration for accurate points Easy export of points in CSV format Easy one-button measurement User-specified amplitude threshold level, or automatic selection Selectable starting BER to increase accuracy when using long patterns, as defined in MJSQ Q-factor Measurement One-button measurement of a vertical cross section through the middle of the eye Easy visualization of system noise effects Export of data in CSV format Compliance Contour Validation of transmitter eye performance to standards such as XFP/XFI and OIF CEI Overlay compliance masks onto measured BER contours and easily see whether devices pass the BER performance level specified www. tektronix. com 17 Data Sheet Error Statistics view showing link performance in terms of bit and burst occurrences. The Pattern Sensitivity view is a powerful way of examining whether error events are pattern related. It shows which pattern sequences are the most problematic, and operates on PRBS and user-defined patterns. Analysis Views Error Statistics: A tabular display of bit and burst error counts and rates Strip Chart: A strip chart graph of bit and burst error rates Burst Length: A histogram of the number of occurrences of errors of different lengths Error Free Interval: A histogram of the number of occurrences of different error-free intervals Correlation: A histogram showing how error locations correlate to user-set block sizes or external marker signal inputs Pattern Sensitivity: A histogram of the number of errors at each position of the bit sequence used as the test pattern Strip Chart view showing bit and burst error performance over time. This can useful while temperature cycling as part of troubleshooting, for example. Block Errors: A histogram showing the number of occurrences of data intervals (of a user-set block size) with varying numbers of errors in them Error Location Capture Error Analysis Error analysis is a powerful series of views that associate error occurrences so that underlying patterns can be easily seen. It is easy to focus in on a particular part of an eye diagram, move the sampling point of the BERTScope there, and then probe the pattern sensitivity occurring at that precise location. [. . . ]