Detailed instructions for use are in the User's Guide.
[. . . ] Bit Error Rate Tester
BitAlyzer® BA Series Data Sheet
BitAlyzer® Error AnalysisTM to Rapidly Understand your BER Performance Limitations, Assess Deterministic versus Random Errors, Perform Detailed Pattern-dependent Error Analysis, Perform Error Burst Analysis, and Error-free Interval Analysis Eye Diagram Display with Automatic Measurements and Fast Eye Mask Testing for Quick Signal Integrity Analysis of the Device Under Test ANSI Jitter Measurements (RJ, DJ, and TJ) to Measure the Impact of Random and Deterministic Jitter on the Total Jitter at BER of 1012 Q-factor Measurement to Swiftly Analyze the Vertical Eye Opening in Terms of BER BER Contour with Automatic Mask Creation to Measure and View the Eye Diagram Opening as a Function of BER Forward Error Correction Emulation for Built-in Verification of FEC Performance on Your Communication System Design
Features & Benefits
Up to 1. 6 Gb/s Pattern Generator/Error Detector for Fast, Accurate Characterization of Digital Communications Signaling Systems PRBS or 8 Mb User-defined Patterns provide the Versatility to Debug or Verify Any Combination of Digital Signaling Built-in Clock Source for Extremely Accurate Timing Adjustable Amplitude, Offset, Logic Threshold, and Termination enable Signaling Variations to Stress Test Your Receiver Designs Differential and Single-ended I/O ensuring Connectivity for a Variety of Communications Bus Standards
Error Mapping provides you with the Debugging Support to Identify the Cause and Location of Signaling Errors
Applications
Semiconductor Characterization Production Eye Mask, BER, and Jitter Testing Satellite Communications System Functional Testing Wireless Communications System Functional Testing Fiber Optic System and Component Testing Forward Error Correction Evaluation
Data Sheet
The Home view is the starting point for the BA1500 and BA1600. The touch-screen buttons on the right-hand side are used to select the view, operating mode, and configuration of the analyzer.
An intuitive user interface allows easy access to the impressive flexibility of the pattern generator and internal clock source.
Unmatched Performance for Greater Insight Into Your Design to Get Your Work Done Faster
The BitAlyzer® Series Bit Error Rate Testers are the industry's best solution to the challenging signal integrity and BER issues faced by designers verifying, characterizing, debugging, and testing sophisticated electronic and communication system designs. The family features exceptional performance in signal generation and analysis, operational simplicity, and unmatched debugging tools to accelerate your day-to-day tasks. The most comprehensive suite of physical-layer test tools available and the intuitive user interface provide easy access to the maximum amount of information.
Simple User Interface
The BA1500 and BA1600 have the most advanced user interface found on any bit error rate tester. [. . . ] Block sizes can be adjusted and histograms show how many times blocks occur with different numbers of errors in them.
define a block size to display a histogram of the number of times blocks occur that have various numbers of errors in them. Cursors can conveniently be used to find out how many blocks have occurred with more than some specific number of errors inside. The maximum block size is 4 billion bits, making this a very powerful analysis for common block sizes.
Block Error Analysis
Many popular systems have performance that is more related to block error rates rather than bit error rates. Q-factor is to the amplitude domain what jitter is to the time domain. It says how clean the vertical
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Bit Error Rate Tester -- BitAlyzer® BA Series
The accuracy of the BER contour improves as the test runs longer. The best predicted BER and sampling location are also shown.
To get better results, BER data above 1e4 BER are not used when predicting deep BER values. The longer the test runs, the more precise the measurements become.
Jitter Peak BER Contour
Bit Error Rate Contour Measurement is part of the Physical Layer option. This analysis computes the bit error rate around the perimeter of the eye opening and fits these results to the expected bit error rate response curves predicted by additive noise. The depth of the contours can then be extrapolated to lower levels than the actual measurement would allow. BER contours are used to identify how much headroom may be present in a system after considering the amount of decision-point variation that might occur. BER contours can also be exported as "golden" masks for mask testing against a known good sample. It provides Random Jitter (RJ), Deterministic Jitter (DJ) and Total Jitter (TJ) measurements automatically, using the fast BER-scan technique. Jitter measurement accuracy is a function of the sample size used, and no competing jitter measurement technique can match the data gathering efficiency of using BERT scan data. More comprehensive BER measurements mean that there are more significant data points to use when extrapolating BER to make precise jitter measurements. The left-hand and right-hand sides of the jitter distribution are measured separately. The center "green" area shows the deterministic jitter between the two outermost Gaussian distributions.
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Data Sheet
Users can set up error correction strengths, interleave depths, and erasure capabilities to match popular hardware correction architectures. One-dimensional correctors allow users to set the number of symbols in an FEC block and the number of possible corrections. One-dimensional correctors can be preceded by a two-dimensional interleave, allowing improved burst error correction capability. Two dimensions of correction can also be used to implement product-array correctors. In this case, the user specifies the number of rows and columns in the product array, along with the correction strength in both dimensions. As errors are found during the test, they are placed into the emulating table according to the interleaving configuration and, as the table fills, each enabled corrector is checked for cases where the number of errors exceeds the correction strength in any FEC codeword. In the case of two-dimensional correctors, users can also set a configuration to use inner code failures as an outer code erasure. [. . . ] This typically takes only a few passes through the user pattern to gain synchronization, and is typically done fast enough to allow user-defined patterns during fiber recirculating loop experiments, or other applications where fast re-synchronization is required. For accuracy, the BitAlyzer can be preloaded with the expected user pattern such that a hardware-accelerated search can be done to find synchronization.
Error Location Analysis
The BitAlyzer family of bit error rate testers have the added capability to study and archive the exact bit location of each error in the data stream. This proven method has been used in applications over the last 10 years to isolate error causes, find correlations, identify interference and, in general, to solve problems. Error Location Analysis can be done easily using the same test setups typically used for regular bit error rate testing.
External Control of Pattern Generator and Error Detector
BER experiments often require gating error measurement, precise timing of re-synchronizations and bursty packet-like data. [. . . ]